Lesson 03: Variables and Data Types

Logic Values

Verilog supports four logic values and eight strengths to model the functionality of real hardware. Two additional unknown logic values (H and L) may occur internal to the simulation but cannot be used for modeling.

Strengths

Verilog has 8 strength levels: 4 drivings, 3 capacitive, and high impedance (no strength). The words strenght0 specifies the strength when the net drivers drive the value 0; strength1 specifies the strength when the net drivers drive the value 1. The capacitive strengths are for trireg nets only.

The table below shows the strengths:

The default strength is a strong drive. For pullup and pulldown gates, the default strength is pull drive; for trireg the default strength is medium capacitive; and for supply nets, the default strength is supply drive.

A net that is not being driven has a high impedance strength, except for tri0 and tri1, which have pull strength; trireg hold their last strength; and supply nets have supply strength.

Proper variable naming is crucial for writing clear Verilog HDL code, readable, and maintainable. A well-structured naming convention helps in understanding the design and debugging issues efficiently. Here are detailed instructions and best practices for naming variables in Verilog HDL.

Basic Rules:

• Alphabet and Numbers: Variable names can include letters (A-Z, a-z), digits (0-9), and the underscore character (_).
• Case Sensitivity: Verilog is case-sensitive. Data, data, and DATA are three different variables.
• Begin with a Letter or Underscore: Names must start with a letter or an underscore. They cannot start with a digit.
• No Special Characters: Special characters other than the underscore are not allowed in variable names.
• Keywords: Do not use Verilog reserved keywords (e.g., module, wire, reg, always) as variable names.

Common Naming Conventions:

• Lowercase with Underscores: Commonly used for signal names and smaller variables.
• CamelCase: Used for module names, task names, and sometimes for variables.
• Uppercase with Underscores: Often used for constants and parameters.

Examples:

• Lowercase with Underscores
  • data_in, data_out, clk, reset_n
  • Example:

    wire data_in;
    wire data_out;
    reg  clk;
    reg  reset_n;

• CamelCase
  • DataIn, DataOut, Clk, ResetN
  • Example:

    wire DataIn;
    wire DataOut;
    reg  Clk;
    reg  ResetN;

• Uppercase with Underscores
  • DATA_WIDTH, ADDRESS_BUS
  • Example:

    parameter DATA_WIDTH = 8;
    parameter ADDRESS_BUS = 16;

Naming Variables by Type:

• Wires: Use names that describe the signal carried by the wire.
• Registers: Use names that describe the stored value or the purpose of the register.
• Parameters: Use uppercase with underscores to define constants.
• Modules: Use CamelCase or descriptive names with underscores.
• Instances: Use the type of module and a suffix to differentiate instances.

Example Code with Naming Conventions:

Module Definition and Instantiation

module FourBitAdder (a, b, sum, carry_out);
    input  [3:0] a;
    input  [3:0] b;
    output [3:0] sum,
    output carry_out;

    assign {carry_out, sum} = a + b;

endmodule

Using the Module

module TopModule ( input_a, input_b, output_sum, output_carry);
    input  [3:0] input_a,
    input  [3:0] input_b,
    output [3:0] output_sum,
    output output_carry;

    FourBitAdder adder_inst (
        .a(input_a),
        .b(input_b),
        .sum(output_sum),
        .carry_out(output_carry)
    );

endmodule

Guidelines for Different Variable Types:

• Inputs and Outputs: Name inputs and outputs to reflect their roles.
  • Example: clk, rst, data_in, data_out

  • module ExampleModule ( clk, rst, data_in, data_out);
        input  clk, rst;
        input  [7:0] data_in,
        output [7:0] data_out;

• Internal Signals: Use descriptive names for internal signals.
  • Example: temp_sum, carry_bit

  • reg [3:0] temp_sum;
    wire carry_bit;

• State Variables: Use clear names for state variables in finite state machines (FSMs).
  • Example: IDLE, PROCESSING, DONE

  • typedef enum reg [1:0] {
        S_IDLE = 2'b00,
        S_PROCESSING = 2'b01,
        S_DONE = 2'b10
    } state_t;
    state_t current_state, next_state;

• Parameters and Constants: Use uppercase with underscores.
  • Example: DATA_WIDTH, MAX_COUNT

  • parameter DATA_WIDTH = 8;
    parameter MAX_COUNT = 255;

Avoiding Common Pitfalls:

1. Avoid Ambiguous Names: Ensure names are not too generic.
   • Bad Example: temp, var
   • Good Example: temp_sum, counter_value
2. Avoid Confusing Names: Ensure variable names do not differ only by case.
   • Bad Example: Data, data
   • Good Example: data_in, data_out
3. Avoid Overly Long Names: While descriptive, do not make names too long.
   • Bad Example: temporary_storage_for_intermediate_sum
   • Good Example: temp_sum
4. Consistent Prefixes: Use prefixes to indicate signal type or scope if helpful.
   • Example: i_ for inputs, o_ for outputs

   • input  i_clk;
     output o_ready;

Example of a Well-Named Verilog Module:

module ExampleModule ( clk, rst_n, data_in, data_out);
    input  clk, rst_n;
    input  [7:0] data_in,
    output [7:0] data_out;

    reg [7:0] data_out;
    // Internal signals
    reg [7:0] buffer;

    // Synchronous logic
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            buffer <= 8'b0;
            data_out <= 8'b0;
        end else begin
            buffer <= data_in;
            data_out <= buffer;
        end
    end

endmodule

Summary:

• Descriptive Names: Ensure names clearly describe the variable’s purpose.
• Consistent Naming Convention: Use a consistent approach to naming variables.
• Short and Meaningful: Keep names concise but meaningful.
• Avoid Abbreviations: Use commonly understood abbreviations if necessary.
• Avoid Keywords and Special Characters: Ensure names are valid and not reserved.

Data Types

Verilog has two major data type classes:

• Net data types are used to make connections between parts of a design.
  • Nets reflect the value and strength level of the net's drivers or the net's capacitance and do not have a value of their own.
  • Nets have a resolution function, which resolves a final value when multiple drivers are on the net.
• Variable data types are used to store programming data temporarily.
  • Variables can only be assigned a value from within an initial procedure, an task, or a function.
  • Variables can only store logic values; they cannot store logic strength.
  • Variables are un-initialized at the start of the simulation and contain a logic x until a value is assigned.

module mux(a, b, out, control);
input   a, b, control;
output  out;

tri     out;

bufif0 B1(out, a, control);     // drives a when control = 0; z otherwise
bufif1 B2(out, b, control);     // drives b when control = 1; z otherwise

supply1     vcc;        // All nets connected to vcc are connected to power supply
supply0     gnd;        // All nets connected to gnd are connected to ground

reg a, b, c;                        // three scalar (1-bit) variables
reg signed [7:0] d1, d2;            // two 8-bit signed variables
reg        [7:0] mem [0:3][0:15];   // a 2-dimensional array of 8-bit variables

integer i, j;                       // two 32-bit signed integer variables
real    r1, r2;                     // two double-precision variables
reg     clk = 0, reset = 1;         // two reg variables with initial values

reg        [7:0] a;
reg signed [7:0] b;
reg        [7:0] c;
reg signed [7:0] d;

initial begin
  a =  -8'd69 ;
  b =  -8'd69 ;
  c =  -8'd69 ;
  d =  -8'd69 ;
  #10;
  $display("a      : %8b, %d", a, a);
  $display("b      : %8b, %d", b, b);
  a = a/2     ;
  b = b/2     ;
  #10;
  $display("a=a/2  : %8b, %d", a, a);
  $display("b=b/2  : %8b, %d", b, b);
  $display("c >>>1 : %8b, %d", c>>>1, c>>>1);
  $display("d >>>1 : %8b, %d", d>>>1, d>>>1);
end

integer counter;                // general purpose variable used as a counter
integer arrayOfInts [1:100];    // integer array

initial
    counter = -1;               // A negative one is stored in the counter

integer A;

initial begin
    A = -12;
    $display("A  : %d %h", A, A);
    A = -32'd12;
    $display("A  : %d %h", A, A);
    A = -12 / 4;
    $display("A  : %d %h", A, A);
    A = -32'd12/4;
    $display("A  : %d %h", A, A);
end

time    sim_time1;      // Define a time variable sim_time1

sim_time1 = $time;      // Save the current simulation time

real    delta;          // Define a real variable called delta
real    pi;             // Define a real variable called pi

initial begin
    delta = 4e10;       // delta is assigned in exponential notation
    pi    = 3.1415;     // pi is assigned a value 3.1415
end

integer i;              // Define an integer i

initial begin
    i = pi;             // i gets the value 3 (rounded value of 3.1415)
end

parameter   PORT_ID = 5;                // Define a constant PORT_ID
parameter   CACHE_LINE_WIDTH  = 256;    // Constant defines width of cache line
parameter   signed [15:0] WIDTH;        // Fixed sign and range for parameter WIDTH

module bus_mux(a, b, sel, out);
    parameter   N = 2;
    input  [N-1:0] a;
    input  [N-1:0] b;
    input  sel;
    output out;
    wire [N-1:0] sel_bus;
    
    assign sel_bus = {N{sel}};              // replicates 2 times
    assign out = (~sel_bus & a) | (sel_bus & b);

endmodule

localparam  S_IDLE  = 4'b0001,
            S_1     = 4'b0010,
            S_2     = 4'b0100,
            S_3     = 4'b1000; 

reg [12*8:1]    str1, str2;

str1 = "EE4480";
str2 = "Verilog";