Page 37 - EE2449_TTL_Datasheet
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SN54/74LS155 • SN54/74LS156



             LOGIC DIAGRAM
                                                       E a E a    A 0  A 1             E b E b
                                                      1    2    13      3            14   15












                               V CC  = PIN 16
                               GND = PIN 8           7    6    5    4    9    10   11   12
                                  = PIN NUMBERS
                                                      O 0a  O 1a  O 2a  O 3a  O 0b  O 1b  O 2b  O 3b


             FUNCTIONAL DESCRIPTION
               The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti-  AND the minterm functions by tying outputs together.  Any
             plexers with common Address inputs and separate gated  number of terms can be wired-AND as shown below.
             Enable inputs. When enabled, each decoder section accepts
             the binary weighted Address inputs (A 0 , A 1 ) and provides four  f = (E + A 0  + A 1 ) ⋅ (E + A 0  + A 1 ) ⋅ (E + A 0  + A 1 ) ⋅
             mutually exclusive active LOW outputs (O 0 –O 3 ). If the Enable  (E + A 0  + A 1 )
             requirements of each decoder are not met, all outputs of that  where E = E a  + E a ; E = E b  + E b
             decoder are HIGH.
               Each decoder section has a 2-input enable gate. The          E              E
             enable gate for Decoder “a” requires one active HIGH input     A 0        O 0  A 0       O 0
                                                                            A 1           A 1
             and one active LOW input (E a •E a ). In demultiplexing applica-
             tions, Decoder “a” can accept either true or complemented      E              E
             data by using the E a  or E a  inputs respectively. The enable gate  A 0  O 1  A 0       O 1
             for Decoder “b” requires two active LOW inputs (E b •E b ). The  A 1         A 1
             LS155 or LS156 can be used as a 1-of-8 Decoder/Demulti-        E              E
             plexer by tying E a  to E b  and relabeling the common connection  A 0    O 2  A 0       O 2
             as (A 2 ). The other E b  and E a  are connected together to form  A 1       A 1
             the common enable.                                             E              E
               The LS155 and LS156 can be used to generate all four         A 0        O 3  A 0       O 3
             minterms of two variables. These four minterms are useful in   A 1           A 1
             some applications replacing multiple gate functions as shown
             in Fig. a. The LS156 has the further advantage of being able to         Figure a



                                                         TRUTH TABLE
                        ADDRESS    ENABLE “a”       OUTPUT “a”        ENABLE “b”       OUTPUT “b”

                        A 0   A 1   E a   E a   O 0  O 1   O 2   O 3   E b  E b   O 0   O 1   O 2   O 3
                         X     X    L     X     H     H     H    H     H     X     H     H    H     H
                         X     X    X     H     H     H     H    H     X     H     H     H    H     H
                         L     L    H     L     L     H     H    H     L     L     L     H    H     H
                         H     L    H     L     H     L     H    H     L     L     H     L    H     H
                         L     H    H     L     H     H     L    H     L     L     H     H    L     H
                         H     H    H     L     H     H     H    L     L     L     H     H    H     L
                      H = HIGH Voltage Level
                      L = LOW Voltage Level
                      X = Don’t Care






                                                    FAST AND LS TTL DATA
                                                            5-151
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