Page 18 - EE2449_TTL_Datasheet

SN54/74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR

The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-
rect Clear inputs. These dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level DUAL JK FLIP-FLOP
of the J and K inputs will perform according to the Truth Table as long as mini- WITH SET AND CLEAR
mum set-up times are observed. Input data is transferred to the outputs on the
LOW POWER SCHOTTKY
HIGH-to-LOW clock transitions.

J SUFFIX
MODE SELECT — TRUTH TABLE CERAMIC
CASE 620-09
INPUTS OUTPUTS
OPERATING MODE
OPERA TING MODE 16 1
S D C D J K Q Q
Set L H X X H L
Reset (Clear) H L X X L H
*Undetermined L L X X H H
N SUFFIX
Toggle H H h h q q
PLASTIC
Load “0” (Reset) H H l h L H CASE 648-08
Load “1” (Set) H H h l H L 16
Hold H H l l q q 1
*Both outputs will be HIGH while both S D and C D are LOW, but the output states are unpredictable
if S D and C D go HIGH simultaneously.
H,h = HIGH Voltage Level D SUFFIX
L,l = LOW Voltage Level SOIC
X = Immaterial 16 CASE 751B-03
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior 1
to the HIGH-to-LOW clock transition

ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
LOGIC DIAGRAM

LOGIC SYMBOL

Q Q 2 7

S D S D
16 K Q 15 12 K Q 11
1 CP 6 CP
CLEAR (C D ) SET (S D )

J K 4 J C D Q 14 9 J C D Q 10
3 8
CLOCK (CP) V CC = PIN 5
GND = PIN 13

FAST AND LS TTL DATA
5-78
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